Our SOI (Silicon-On-Insulator) wafers combine a top device silicon layer,buried oxide (BOX) layer, and handle silicon layer, available in diameters from 2" to 8". With tightly controlled thickness tolerances(±5%), low TTV (<5μm) and bow (<20μm), plus flexible doping options(P-type, N-type, intrinsic) and resistivity from 0.001 to over 20,000 Ω·cm, our SOI wafers deliver reliable performance for CMOS,RF, MEMS, and power semiconductor applications.

Applications

- Advanced CMOS logic and low-power ICs

- RF front-end and high-frequency devices

- MEMS sensors and actuators

- Power semiconductor devices requiring dielectric isolation

Why Choose Us? 

- Precise thickness control for the three‑layer structure, with tolerance stably maintained within ±5%. 

- Total Thickness Variation (TTV) is less than 5 μm and warpage below 20 μm, ensuring consistent performance for downstream photolithography processes. 

- Customizable doping types and resistivity ranges to accommodate diverse process requirements. 

- Full‑size coverage from 2‑inch to 8‑inch, supporting both R&D prototyping and mass production.